Area-throughput trade-offs for fully pipelined 30 to 70 Gbits/s AES processors
نویسندگان
چکیده
منابع مشابه
Speed-Area Trade-off for 10 to 100 Gbits/s Throughput AES Processor
This paper explores the area-throughput trade-off for an ASIC implementation of the Advanced Encryption Standard (AES) algorithm in a 0.18 μm CMOS technology. Three different pipelined implementations of the AES algorithm are presented which provide a throughput range between 15.7 to 77.6 Gbits/s with an area cost of 116 to 473 Kgates. Therefore, the AES algorithm in the counter mode of operati...
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ژورنال
عنوان ژورنال: IEEE Transactions on Computers
سال: 2006
ISSN: 0018-9340
DOI: 10.1109/tc.2006.49